Our AMS team has deep domain expertise in the areas of High Speed Interfaces, Analog Signal Processing and Power Management.
Our non-core analog activities include Modeling & Library services including IO, PDK and standard cell libraries. We leverage our experience of working with a wide range of Fabs and technology nodes to help reduce the full chip level simulation time by creating accurate analog models at the block and full chip levels.
| Expertise Areas | Process Experience |
Power Management - Frameworks for low (1V) Turn-On voltage circuits
- High efficiency & low EMI noise
- Variety of regulators; references;
Protection circuits - Minimizing off-chip components
- Area efficient power switch layouts
Signal Processing - Architectures for low supply/
Wide supply range - High sampling rate (4MSPS) for a given resolution (10bits)
- Re-usable frameworks &
Proven development models - Low noise designs & Sensor interface
High Speed Interfaces - High speed serial link for video data transfer/receive
- High precision 5x oversampling CDR;
BER of 10e-12 - Silicon proven LVDS IP Core
- Area & Power Efficient LF SSC Generator
| Generic 40nm to .45 microns CMOS - Generic process for Analog & Custom Digital blocks
- Supply voltages < 1V to 6V
High Voltage 0.15 microns to 0.45 microns - BCDMOS & High voltage CMOS
- Supply voltages 15V / 24V / 40V / 65V
Customized 45nm to .45 microns CMOS
- Special application dependent processes
- Low power & Low leakage, High speed
- Supply voltages 1V to 5.5V
Our Bench Testing Lab Characterization of PLLs & Clock circuits - Frequency of Operation: up to 100MHz
- Jitter: > 250ps (Sampling rates up to 4 Gsps)
Characterization of Power management chips - Switching & linear regulators
- Line & load regulation
- Output ripple & efficiency
- Voltage up to 25V, Current range up to 5A
Characterization of DATA Converter circuits - Linearity, Accuracy until 5mV
- Up to 12 Bits of operation, Clock rate up to 50MHz
- Freq. of operation: 1.0MHz
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Our Digital Design capabilities include Core Integration, Verification, Physical Design and Design for test. Learn More.
We understand that a ready IP helps in faster realization of products. With our continuous investments in research and development activities over the years have developed IP`s that provide ready to use solutions.
We also engage with our customers in joint IP programs to minimize their risk and lower their investments.
LVDS/CMOS PHY High Speed SERDES Link
A Multi IO mode for LVDS/CMOS, configurable, low EMI, compliant with TIA/EIA 644-A standards, that is suitable for point-to-point data transmission for automotive and consumer applications.
Microphone Pre-Amplifier
The microphone preamplifier is a low noise, high performance signal processing macro for where signal is pre-amplified before fed to further processing and a charge-pump for high voltage microphone biasing. This microphone gives clear and good audio quality. Preamplifier has a gain Programmability option which can be used to compensate the variation in microphone sensitivity levels.
10 bit 205Msps Pipeline ADC
High performance CMOS analog to digital converter that digitizes signals at sampling rates upto 205Msps and converts to 10-bits resolution at 205Msps at a very low power of 250mW typical. The reference voltages are internally generated. A power down capability is provided for low power dissipation in stand-by mode. The ADC cell is useful for video and graphics applications.
16 bit sigma delta ADC
High performance CMOS analog to digital converter that digitizes signals of bandwidth upto 20kz can be configured for instrumentation or audio application
Voltage Controlled Delay Line (VCDL)
Voltage Controlled Delay Line (VCDL) generates precise delay where required delay can be chosen at different output taps based on control bits setting. This delay line gives precise delay at very low power consumption.
Multi-level signal Transmitter
The MCML transmitter is Gigabit, high speed transmitter used in serial communication link. This block enables much smaller transmit swing and hence consumes very low power. Alternatively, this circuit improves bit error rate (BER) significantly by precisely controlling output transmit swing.
Phase Locked Loop 5MHz-100MHz
This IP is a Wide Band CMOS Phase locked loop which generates 5MHz to 100MHz with 14 phases. This PLL is a simple Integer-N based and targeted at High speed SERDES links with different data rate requirements.
Band Gap Reference
This is a Band Gap reference IP for accurate Voltage and Current reference. Targeted voltage of 1.2 V +- 2% and Reference Current 20UA +- 10% is generated across Process, Voltage and Temperature.
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