Core Integration
With a vision to be the technology leaders we endeavor to upgrade our technology prowess and capabilities. Being accredited as a design center for ARM, we service all our customers' core integration needs, be it proprietary or standard cores.
Expertise
- Part of Core Architecture Exploration Team
- Design, Verification & Integration
- Peripheral and System Legacy RTL Migration to AMBA Standards
- Develop Peripheral Interfaces on AMBA Standards - AHB, APB, AXI
- Custom Emulation Platforms
- Porting RTL to Standard Platforms
- Verification at Board Level using System Testing methods and Debuggers on FPGA Platforms
Verification
With an expertise spanning 600+ man years and experience of creating multiple designs of extreme complexity, we are well equipped to keep our customers' designs bug free and ensure first pass silicon.
Areas of Work
- Development of methodologies & framework for conventional and constraint random verification
- Block, cluster & full chip level verification
- Automated test benches & regression environment
- Development of verification IP's compliant to eRM / OVM / VMM etc.
- Co-Verification (ISX, VaST) and formal (IFV) verification
- Complete low power design methodology expertise using cadence CPF and synopsys UPF
- Development of regression suites in Specman Elite, C/C++, Vera, System Verilog, SystemC etc.
- Expertise in mixed signal verification
Physical Design
With an expertise spanning over 100+ man years and experience of taping out multi-million gate, multiple designs in different technologies ranging from 45nm to 180nm, we are well equipped to implement high quality designs of varying complexities that are delivered on schedule.
Areas of Work
- Wire bond and flip chip design implementation
- High frequency designs as well as low power designs
- Physical implementation of designs using Synopsys, Cadence and Magma flows
- Design implementation using in-house design flows
- IO frame generation
- Bonding feasibility analysis to satisfy the ESD and SSO rules
- ARM core hardening
Design for Test
Our design for test group has experience on a range of technologies and EDA tools that enable us to provide the best of services.
Expertise
- Defining of test concepts and specifications
- Architecting of complete IC test
- Plan for low DPPM and higher yield
- Test time reduction techniques
- Scan compression(XOR, MISR), Logic Bist , ATPG(stuckat, Transition(LOC/LOS), Path Delay, IDDQ)
- At speed memory bist and repair
- Reliability test
- Power management for test
- ARM based functional tests for fault grading
Our Analog Mixed Signal expertises include Power Management, Signal Processing and High Speed Interfaces. Learn More.
We understand that a ready IP helps in faster realization of products. With our continuous investments in research and development activities over the years we have developed IPs that provide ready to use solutions.
We also engage with our customers in a joint IP programs to minimize their risk and lower their investments.
System Logic IP
We possess unique capabilities to develop complex system logic related IP blocks such as Clock and Reset Controller, and Power Management Controller. These can be adapted to suit varied customer requirements, including on-the-fly clock frequency adjustments, and low power frameworks. Power Management Controller can be built to work with external power management units, or using internal power switches. Implementation of power reduction schemes can be tied to industry leading methodologies such as CPF or UPF, or can also be performed in RTL, to allow for legacy verification approaches.
HS SPI Design IP
The Serial Peripheral Interface (SPI) is the de facto standard developed by Motorola. The legacy SPI is full duplex serial interface, designed to handle the Master and Slave connected to the bus. Only single Master and Slave can communicate on the interface during a given data transfer. The latest memory devices support high speed, half duplex, and dual/quad bit modes of operation (called High Speed SPI).
10G Ethernet MAC (XGMAC) Design IP
The IP core implements 10-Gigabit MAC and Reconciliation Sub-Layer (RS) as specified in the IEEE 802.3-2005 specification. The RS has MAC as its client and PHY Layer below it. The RS will interact to lower PHY layer on an interface called as XGMII defined in the standard. The RS to MAC interface is implementation specific.
Interrupt Controller Design IP
The Interrupt controller (IC) used in ARM based MCU, supports up to 512 normal interrupt sources (IRQ) and up to 32 non maskable interrupt sources (NMI). All IRQ sources are processed to generate single interrupt (nIRQ) to the processor. All NMI sources are processed to generate single interrupt (nFIQ) to the processor. The IRQ interrupts are maskable and support software interrupts, priority filtering and vector generation. The NMI interrupts are non-maskable and support software interrupts, priority filtering and vector generation.
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